1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to a semiconductor device provided with a mounting board or a package substrate having a power-supply plane, a ground plane, and a dielectric layer disposed therebetween.
2. Description of the Related Art
Following recent increase in operation speed and reduction in power consumption of semiconductor devices, noise generated between the power supply and the ground of the mounting board or package substrate increases its effect on transmission of signals.
Simultaneous switching noise is referred to as an example of the noise generated between the power supply and the ground. The simultaneous switching noise has conventionally been addressed by enlarging the area of the power-supply plane or ground plane, or by mounting a bypass capacitor. However, the increase in operation speed of a semiconductor device results in reduced size and increased density of the semiconductor device. As a consequence, it is difficult to ensure a sufficient area for the power-supply plane and the ground plane or to arrange a required number of bypass capacitors. Therefore, other effective methods than these are required to reduce the noise between the power supply and the ground.
There is conventionally known a multi-layer wiring board capable of suppressing noise due to resonance of the power supply or ground plane. In such as board, an insulating layer formed of an insulating material having a high dielectric loss tangent is provided between a plane conductor for forming power supply wiring and another plane conductor for forming ground wiring (see, for example Japanese Laid-Open Patent Publication No. 2005-129619 (Patent Document 1)).
There is also known an electronic component in which a conduction noise inhibitor for suppressing conduction noise possibly causing radiation noise is arranged between a power supply layer and a ground layer of a multi-layer wiring board (see, for example, Japanese Laid-Open Patent Publication No. 2006-140430 (Patent Document 2)).